LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY control IS
	PORT ( clock								: IN STD_LOGIC;
		start 									: IN STD_LOGIC;	
		TorD 									: IN STD_LOGIC;	
		tagCtrlIn 								: IN STD_LOGIC;	
		switchRdy 								: IN STD_LOGIC;	
		finish									: OUT STD_LOGIC;
		inputEnable								: OUT STD_LOGIC;
		inputReset								: OUT STD_LOGIC;
		vlanReset								: OUT STD_LOGIC;
		vlanEnable								: OUT STD_LOGIC;
		lutReset								: OUT STD_LOGIC;
		lutEnable								: OUT STD_LOGIC;
		tagGenEnable							: OUT STD_LOGIC;
		tagCtrlOut								: OUT STD_LOGIC;
		TorDout									: OUT STD_LOGIC;
		vlanRdy									: OUT STD_LOGIC := '1';
		x8100									: OUT STD_LOGIC_VECTOR(15 downto 0) := "1000000100000000" );
END control;

ARCHITECTURE arch OF control IS
	
	
	TYPE State_type IS (A,B,C,D,E,F,Z1,Z2);
	SIGNAL y 	: State_type;
	
	
	--constant aluADD	: std_logic_vector(2 downto 0) := "000";

	
BEGIN

	PROCESS (clock, start)
	BEGIN
		IF (clock'EVENT and clock = '1')THEN
			CASE y IS
				WHEN A => --this case is used to intially start the system
				--might need more reset conditions
						lutReset <= '0';
						IF start = '1' THEN
							inputEnable <= '1';
							inputReset <= '1'; 
							vlanRdy <= '0';
							y <= B;
						ELSE y <=A;
						END IF;
						
				WHEN B =>
						 
						inputEnable <= '0'; --stop incoming from overwriting
						lutEnable <= '1';--send mac addresses through LUT
						--delay stages for LUT
						y <= Z2;
						--y <= C;
						
				WHEN C => 
						vlanEnable <= '1';
						vlanReset <= '1';
						lutEnable <= '0';
						tagGenEnable <= '1';
						--delay stages
						y <= D;
						--y <= E;
						
				WHEN D => 
						vlanEnable <= '0';
						
						--delay stages
						y <= E;
						
				WHEN E => 
						IF TorD = '0' THEN
							finish <= '1';
							IF tagCtrlIn = '1' THEN
								tagCtrlOut <= '1';
							END IF;
						ELSE TorDout <= '1';
						END IF;
						y <= Z1;
						
				
				WHEN F => --reset state
						inputReset <= '0'; 
						lutReset <= '1'; 
						--lutReset <= '0'; 
						vlanReset <= '0';
						tagGenEnable <= '0';
						finish <= '0';	
						tagCtrlOut <= '0';	
						TorDout <= '0';	
						vlanRdy <= '1';
						y <= A;
						--wait for next input

				WHEN Z1 =>
						IF switchRdy = '1' THEN
							y <= F;
						ELSE
							y <= Z1;
						END IF;
						--maybe more delay for switch to read
						
				WHEN Z2 =>
						y <= C;

			END CASE;
		END IF;
	END PROCESS;						
	
END arch;